The present invention relates to a semiconductor device including a protecting circuit which is capable of preventing the semiconductor device from a rapid surge. The present invention is applicable to insulated gate transistors, such as power metal oxide semiconductor field effect transistors (abbreviated MOSFETs) and insulated gate bipolar transistors (abbreviated IGBTs).
FIG. 22 shows a conventional semiconductor device. A protecting apparatus of this conventional semiconductor device comprises a serial circuit 3 consisting of a plurality of clamping Zener diodes. The serial circuit 3 is connected between drain and gate electrodes of a double diffused metal oxide semiconductor (DMOS) field-effect transistor 2 which is actuated by a gate actuating circuit 8. The purpose of providing the serial circuit 3 is to improve the surge durability against a surge voltage caused by an inductive load 1.
According to the circuit arrangement shown in FIG. 22, when the semiconductor device receives a surge voltage applied from the inductive load 1, each Zener diode in the serial circuit 3 causes breakdown at a predetermined voltage level lower than that of the field-effect transistor 2. Thus, the field-effect transistor 2 turns on in response to electric charge input to the gate electrode thereof. Surge current, corresponding to the surge voltage, flows through the field-effect transistor 2. In the following description, the field-effect transistor is referred to or abbreviated as FET.
As the operation resistance of FET 2 has a positive temperature coefficient, no current concentration occurs. Accordingly, FET 2 causes no internal breakdown. A parasitic transistor 2a of FET 2 does not operate. The surge durability of the semiconductor device is improved.
In this semiconductor device, each Zener diode in the serial circuit 3 may be a multiple polysilicon Zener diode including alternately doped boron and phosphor, or a multiple Zener diode formed by diffusing base and emitter layers in a power integrated circuit.
Thus, the Zener diodes are not large in chip size. The overall size of the Zener diodes is generally small compared with that of FET 2.
The internal resistance of all Zener diodes in the serial circuit 3 is usually a large value equal to approximately 1 kΩ. To allow the current to smoothly flow, it is necessary to maintain breakdown voltage of each Zener diode (which is usually 10V lower than the withstand voltage of FET 2). Thus, a sufficiently large bias cannot be applied to the gate electrode of FET 2. Hence, a current amount flowing in response to the turning-on operation of FET 2 is small. In other words, it is difficult to sufficiently improve the durability against a rapid and large-current surge caused by an electrostatic discharge (abbreviated ESD, hereinafter).
FIG. 23 shows a conventional semiconductor device proposed in the Unexamined Japanese patent publication No. 8-64812.
According to the circuit arrangement shown in FIG. 23, a protecting circuit 4, a back-flow preventing Zener diode 5 and a resister 6 are connected between an inductive load 1 and the gate electrode of FET 2.
The protecting circuit 4 includes a DMOS-FET 4a. This FET 4a has a drain electrode connected to a drain electrode of FET 2 and a source electrode connected via the Zener diode 5 and the resister 6 to the gate electrode of FET 2.
Furthermore, the protecting circuit 4 includes a capacitor 4b which is connected between the gate and drain electrodes of FET 4a. The capacitor 4b is connected in parallel with a serial circuit which consists of a plurality of clamping Zener diodes 4c connected in series. A resister 7 is interposed between the gate and source electrodes of FET 4a. 
When a surge voltage caused by the inductive load 1 is applied to the protecting circuit 4, the surge current passes the capacitor 4a and flows into the gate electrode of FET 4a. Thus, FET 4a turns on in the initial stage.
In response to the turning-on operation of FET 4a, the surge current based on the surge voltage caused by the inductive load 1 flows into the gate electrode of FET 2 via FET 4a, Zener diode 5 and the resister 6, so as to turn on FET 2. Thus, the surge current flows across FET 2 from the inductive load 1.
However, when the surge voltage is an ESD surge causing rapid and large current (having operation time of approximately 10 nsec, peak current of approximately 160 A, 150Ω, 150 pF, and 25 kV discharge), it is necessary to quickly increase the gate potential of FET 2 to a higher level (e.g., 10 times the threshold value of FET 2) in a short time (e.g., within 1 nsec) by turning on FET 4a. When FET 2 turns on, the surge current flows across FET 2.
However, as described above, the resister 6 is interposed between the Zener diode 5 and the gate electrode of FET 2. The resister 6 limits the charge current flowing into the gate electrode of FET 2. Thus, it becomes impossible to quickly and sufficiently charge the gate electrode of FET 2.
Accordingly, there is the possibility that the internal diode of FET 2 induces avalanche breakdown. In a worst case, the parasitic bipolar transistor of FET 2 may operate and induce permanent damage due to current concentration. As a result, the ESD durability of FET 2 (or the semiconductor device) may deteriorate.